1. Field of the Invention
The present invention relates in general to the manufacture of semiconductor integrated circuits. More particularly, it relates to a dual damascene process for preventing photoresist contamination.
2. Description of the Related Art
In the semiconductor industry, much effort is spent developing semiconductor devices with high operating speeds. Due to rapid progress in integrated circuit (IC) fabrication technologies, the integration of the IC devices has increased, and raising the resistance of metal wires and the parasitic capacitance effect therebetween. The metal wires thus carry a current flow at a low speed. In order to reduce resistance and parasitic capacitance, low resistance material, such as copper, is used for metal wires, and low dielectric constant (low-k) materials are used for the insulating layer between the metal wires.
Recently, a dual damascene process using low-k dielectrics and low resistance metals has been developed to form high-reliability, low cost interconnects in the IC devices. FIGS. 1a though 1d illustrate a conventional method for forming a dual damascene structure. In FIG. 1a, a semiconductor substrate 100 is provided. A sealing layer 102, a low-k dielectric layer 104, and a mask layer 106 with a plurality of trench openings 106a are sequentially formed on the substrate 100.
In FIG. 1b, a photoresist layer 108 has been coated on the mask layer 106 and filled into the openings 106a. Next, lithography is performed on the photoresist layer 108, thereby forming a patterned photoresist layer 108 with a plurality of via openings 108a aligned with the trench openings 106a overlaying the mask layer 106 and part of the dielectric layer 104. Hence, however, photoresist contamination occurs due to amino elements in the dielectric layer 104. As a result, sidewalls of the patterned photoresist layer 108 have poor profile.
In FIG. 1c, the dielectric layer 104 is anisotropically etched using the patterned photoresist layer 108 as a mask, and the via pattern is then transferred into the upper half of the dielectric layer 104.
In FIG. 1d, the photoresist layer 108 is removed. Thereafter, the dielectric layer 104 is etched using the mask layer 106 with trench openings 106a, and using the sealing layer 102 as an etching stop layer. As a result, trench patterns are transferred into the upper half of the dielectric layer 104, and the via patterns in the upper half of the dielectric layer 104 are simultaneously transferred into the lower half of the dielectric layer 104. These trenches 104b and vias 104a formed in the dielectric layer 104 create a plurality of dual damascene structures. Next, the sealing layer 102 below the vias 104a is removed. Due to photoresist contamination mentioned above, a poor via profile in dual damascene structure results, and low IC device reliability results.
Accordingly, an object of the invention is to provide a dual damascene process for forming an additional cap layer on the dielectric, thereby preventing potentially contaminating photoresist contact with the dielectric layer.
Another object of the invention is to provide a dual damascene process for forming a cap layer as an anti-reflective layer (ARL) to improve the dual damascene structure profile.
To achieve these and other advantages, the invention provides a method of fabricating a dual damascene structure. First, a substrate having a dielectric layer is provided. A cap layer is formed on the dielectric layer, and a mask layer with at least one trench pattern is then deposited overlaying the cap layer. Thereafter, a photoresist layer with at least one via pattern aligned with the trench pattern is formed overlaying the mask layer and part of the cap layer. Next, the via pattern is transferred into the cap layer and the upper half of the dielectric layer. The photoresist layer is then removed. Subsequently, the trench pattern is transferred into the cap layer and the upper half of the dielectric layer, and simultaneously the via pattern in the upper half of the dielectric layer is transferred into the lower half of the dielectric layer. Finally, the trench and the via in the dielectric layer are filled with a conductive layer. In the invention, the cap layer is undoped silicate glass (USG), SiC or SiF, and chemical vapor deposition (CVD) using SiH4 or tetraethyl orthosilicate (TEOS) as a reaction gas.